Digital_Lab_01
"Displaying the input signal value on the 7-segment LED display"
by
Choon B. Kim, Ph.D., a retired ASIC engineer
1. Design Specifications:
1.1) Your design
1.2)
1.4) The design
Input
Output
SW[3:0] HEX3HEX2 HEX0
-----------------------------------------------------------------
0000
00
0
0001
01
1
0010
02
2
0011
03
3
.....
1000
08
8
1001
09
9
1010
10
A
1011
11
b
// <--- Use lower case b here
1100
12
C
1101
13
d
// <--- Use lower case d here
1110
14
E
1111
15
F
-----------------------------------------------------------------
2. Testing (video on YouTube):
Test case:
Display several numbers at random.
https://youtube.com/shorts/wBt2IUy_kp0
3. Recommended additional work:
Add an input value checking feature to above Lab by doing followings.
Connect an LED light(e.g., green color) to the board IO port(e.g., GPIO).
It's ON if (input value) >= A in hex(=10 in decimal).
Test video: https://youtube.com/shorts/3sD4bnBQGa4
4. Key lesson(s) learned from this Lab:
- Basic digital design flow with FPGA board, EDA SW, HDL(Verilog, SystemVerilog, VHDL, etc.) and its synthesizable set.
DESIGN => VERIFICATION => SYNTHESIS => PROGRAMMING FPGA => TESTING & DEBUGGING CYCLE
- Basic combinational circuit design skill
5. Timing(optional):
Assuming your design is used as a part of a bigger clock-based system, find the maximum clock frequency of your design.
Explain how you get it.
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